Process Variation Tolerant VLSI Designs

Name: Process Variation Tolerant VLSI Designs
Brand: OMNIScriptum
SKU: 6049166748
Price: 1024 RUB
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6049166748

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9783659648946

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мягкий

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Т8 Издательские Технологии

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Печатная книга «Process Variation Tolerant VLSI Designs» в мягкой обложке, язык - английский. В книге 80 страниц, она напечатана на белой офсетной бумаге плотностью 80 г/м². Формат издания — 152x229 мм. Все книги аккуратно упаковываем в прочный трёхслойный непрозрачный картонный конверт.
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.